9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire z, x,c,v,n;
    // TODO: instantiate required gates
    not_gate n1(b,z);
    not_gate n2(a,x);
    and_gate a1(a,z,c);
    and_gate a2(b,x,v);
    or_gate or1(c,v,y);
endmodule