9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire n1,n2,n3,n4;
    not_gate xor1(b,n1);
    not_gate xor2(a,n2);
    and_gate xor3(a,n1, n3);
    and_gate xor4(b,n2,n4);
    or_gate xor5(n3,n4,y);

    // TODO: instantiate required gates

endmodule