9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a&b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
wire w1,w2,w3,w4;
    not_gate n1(.a(a), .y(w1)); // w1 = ā
    not_gate n2(.a(b), .y(w2)); // w2 = b̅

    // AND gates
    and_gate a1(.a(a),  .b(w2), .y(w3)); // a·b̅
    and_gate a2(.a(w1), .b(b),  .y(w4)); // ā·b

    // OR gate
    or_gate o1(.a(w3), .b(w4), .y(y));
    
    // TODO: declare intermediate wires

    // TODO: instantiate required gates

endmodule