9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y=a | b;
    // write code here for or gate

endmodule

module not_gate(input a, output y);
    assign y=~a;
    // write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire m[3:0];
    not_gate u0(a,m[0]);
    not_gate u1(b,m[1]);
    and_gate u2(a,m[1],m[2]);
    and_gate u3(b,m[0],m[3]);
    or_gate u4(m[2],m[3],y);

    // TODO: instantiate required gates

endmodule