9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;    // OR gate logic
endmodule

module not_gate(input a, output y);
    assign y = ~a;       // NOT gate logic
endmodule

// ============================================================
// XOR Gate using basic gates
// ============================================================
module xor_gate (
    input  a, b,      // 1-bit inputs
    output y          // 1-bit output
);
    // Declare intermediate wires
    wire nota, notb;
    wire and1, and2;

    // Instantiate NOT gates
    not_gate n1 (.a(a), .y(nota));
    not_gate n2 (.a(b), .y(notb));

    // Instantiate AND gates
    and_gate a1 (.a(nota), .b(b), .y(and1));
    and_gate a2 (.a(a), .b(notb), .y(and2));

    // Instantiate OR gate for final XOR output
    or_gate o1 (.a(and1), .b(and2), .y(y));

endmodule