// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y= a |b;
endmodule
module not_gate(input a, output y);
assign y=~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire a_bar,b_bar,a1,a2;
not_gate n1(a,a_bar);
not_gate n2(b,b_bar);
and_gate ag1(a,b_bar,a1);
and_gate ag2(b,a_bar,a2);
or_gate o1(a1,a2,y);
endmodule