9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = !a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire na,nb,a_nb,na_b;
    // TODO: instantiate required gates
    not_gate n0(a, na);
    not_gate n1(b, nb);
    and_gate a0(a, nb, a_nb);
    and_gate a1(na, b, na_b);
    or_gate o0(a_nb, na_b, y);

endmodule