9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y= ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    wire w1,w2,w3,w4;
    not_gate U1(a,w1);//~a
    not_gate U2(b,w2);//~b;
    and_gate U3(a,w2,w3); //w3=a&w2
    and_gate U4(b,w1,w4);
    or_gate U5(w3,w4,y);
endmodule