9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (input  a, b, output y);
    // TODO: declare intermediate wires
    wire na, nb, t1, t2;
    not_gate u_na(.a(a), .y(na)); // y = ~a
    not_gate u_bn(.a(b), .y(nb)); // y = ~b

    and_gate u_t1(.a(a), .b(nb), .y(t1)); // y = a.b'
    and_gate u_t2(.a(na), .b(b), .y(t2)); // y = a'.b

    or_gate u_y(.a(t1), .b(t2), .y(y)); // y = t1 | t2

    // TODO: instantiate required gates

endmodule