9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire p,q,r,s;

    // TODO: instantiate required gates
    not_gate p1 (a,p);
    not_gate q1 (b,q);
    and_gate r1 (a,q,r);
    and_gate s1 (b,p,s);
    or_gate y1 (r,s,y);

endmodule