9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire nota; // ~a
    wire notb; // ~b
    wire t1; // (a & ~b) 
    wire t2; // (~a & b)

    not_gate n1 (.a(a), .y(nota));
    not_gate n2 (.a(b), .y(notb));
    
    and_gate a1 (.a(a), .b(notb), .y(t1));
    and_gate a2 (.a(nota), .b(b), .y(t2));
    
    or_gate  o1 (.a(t1), .b(t2), .y(y));

endmodule