How do you plan to solve it?
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y = a | b;
endmodule
module not_gate(input a, output y);
assign y=~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire w1, w2; // !a, !b
wire w3, w4; // a.!b, !a.b
not_gate n1 (.y(w1), .a(a));
not_gate n2 (.y(w2), .a(b));
and_gate a1 (.y(w3), .a(a), .b (w2));
and_gate a2 (.y(w4), .a(w1), .b (b));
or_gate o1 ( .a(w3), .b(w4), .y(y));
endmodule