// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y = a | b;
endmodule
module not_gate(input a, output y);
assign y = ~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire na, nb, w1, w2;
not_gate l1 (a, na);
not_gate l2 (b, nb);
and_gate g1 (a, nb, w1);
and_gate g2 (na, b, w2);
or_gate k1 (w1, w2, y);
endmodule