9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire f1, f2, nota, notb;
    // TODO: instantiate required gates
    not_gate NOT1 (.a(a), .y(nota));
    not_gate NOT2 (.a(b), .y(notb));
    and_gate AND1 (.a(a), .b(notb), .y(f1));
    and_gate AND2 (.a(nota), .b(b), .y(f2));
    or_gate OR (.a(f1), .b(f2), .y(y));
endmodule