9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w1, w2;
    wire not_a, not_b;
    // TODO: instantiate required gates
    assign not_a = ~a;
    assign not_b = ~b;
    assign w1 = a & not_b;
    assign w2 = not_a & b;
    assign y= w1 | w2;
endmodule