9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire nota, notb;
    wire w1, w2;
    // TODO: instantiate required gates
    // Inverters
    not_gate n1 (.a(a), .y(nota));
    not_gate n2 (.a(b), .y(notb));

    // AND gates
    and_gate a1 (.a(a),    .b(notb), .y(w1));   // a · b'
    and_gate a2 (.a(nota), .b(b),    .y(w2));   // a' · b

    // OR gate
    or_gate o1 (.a(w1), .b(w2), .y(y));
    

endmodule