9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;
    // write code here for or gate

endmodule

module not_gate(input a, output y);
    assign y = ~a;
    // write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    not_gate u1(b,b1);
    not_gate u2(a,a1);

    and_gate u3(a,b1,c1);
    and_gate u4(b,a1,c2);

    or_gate u5(c1,c2,y);
    // TODO: declare intermediate wires

    // TODO: instantiate required gates

endmodule