9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y= a |b;


endmodule

module not_gate(input a, output y);
    // write code here for not gate
 assign y =~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    not_gate n1 (.a(a),.y(nota));
    not_gate n2 (.a(b),.y(notb));
    and_gate a1 (a,notb,y1);
    and_gate a2 (b,nota,y2);
      // TODO: declare intermediate wires
      or_gate o1(y1,y2,y);

    // TODO: instantiate required gates

endmodule