How do you plan to solve it?
build the gates, instantiate the gates, run the code, win
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y = a||b;
endmodule
module not_gate(input a, output y);
assign y = !a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
// TODO: declare intermediate wires
wire anb, nab, nb, na;
// TODO: instantiate required gates
not_gate z (b,nb);
not_gate t (a,na);
and_gate c (a,nb,anb);
and_gate d (b,na,nab);
or_gate e (anb,nab,y);
endmodule