9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = !a ;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire nota;
    wire notb;
    wire a_and_notb;
    wire nota_and_b;
    // TODO: instantiate required gates
    not_gate a_not (.a(a),.y(nota));
    not_gate b_not (.a(b),.y(notb));

    and_gate ve1 (.a(a),.b(notb),.y(a_and_notb));
    and_gate ve2 (.a(nota),.b(b),.y(nota_and_b));

    or_gate veya1 (.a(a_and_notb),.b(nota_and_b),.y(y));

endmodule