9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    or or1(y,a,b);
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    not n1(y,a);
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire not_b,not_a,not_a_b,not_b_a;
    // TODO: instantiate required gates
    not_gate not1(.a(a),.y(not_a));
    not_gate not2(.a(b),.y(not_b));
    and_gate and1(.a(a),.b(not_b),.y(not_b_a));
    and_gate and2(.a(not_a),.b(b),.y(not_a_b));
    or_gate or1(.a(not_a_b),.b(not_b_a),.y(y));
endmodule