9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
   assign y=a|b; // write code here for or gate

endmodule

module not_gate(input a, output y);
   assign y=~a; // write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
 wire a1,a2,a3,a4,o1,o2;   // TODO: declare intermediate wires
 not_gate g1(.a(b),.y(a2));
 not_gate g2(.a(a),.y(a3));
 and_gate g3(.a(a),.b(a2),.y(o1));
 and_gate g4(.a(a3),.b(b),.y(o2));
 or_gate g5(.a(o1),.b(o2),.y(y));

    // TODO: instantiate required gates

endmodule