9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate

endmodule

module not_gate(input a, output y);
    // write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire notA, notB, w1, w2;
    assign notA = !a;
    assign notB = !b;
    assign w1 = a & notB;
    assign w2 = b & notA;
    assign y = w1 | w2;
    // TODO: instantiate required gates

endmodule