9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y=a|b;// write code here for or gate

endmodule

module not_gate(input a, output y);
    assign y=~a;// write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
wire na,nb,y1,y2;
    // TODO: instantiate required gates
not_gate n1(.a(a),.y(na));
not_gate n2(.a(b),.y(nb));
and_gate n3(.a(a),.b(nb),.y(y1));
and_gate n4(.a(na),.b(b),.y(y2));
or_gate n5(.a(y1),.b(y2),.y(y));

endmodule