9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire ANot, BNot, y1, y2;
    // TODO: instantiate required gates
    not_gate A    (.a(a), .y(ANot));
    not_gate B    (.a(b), .y(BNot));
    and_gate AND1 (.a(a), .b(BNot), .y(y1));
    and_gate AND2 (.a(ANot), .b(b), .y(y2));
    or_gate  OR   (.a(y1), .b(y2), .y(y));
endmodule