9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a|b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire abn, anb, inva, invb;
    // TODO: instantiate required gates
    not_gate invA   (a, inva);
    not_gate invB   (b, invb);
    and_gate and1   (a, invb, abn);
    and_gate and2   (inva, b, anb);
    or_gate  out    (abn, anb, y);
endmodule