9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire nota,notb,w1,w2;
    // TODO: instantiate required gates
    not_gate g1(.a(a),.y(nota));
    not_gate g2(.a(b),.y(notb));

    and_gate g3(.a(a),.b(notb),.y(w1));
    and_gate g4(.a(nota),.b(b),.y(w2));

    or_gate g5(.a(w1),.b(w2),.y(y));
    

endmodule