9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire interm1, interm2;
    wire a_bar, b_bar;

    not_gate not1 (a, a_bar);
    not_gate not2 (b, b_bar);

    and_gate and1 (a,b_bar,interm1);
    and_gate and2 (a_bar,b,interm2);

    or_gate or1 (interm1,interm2,y);

    // TODO: instantiate required gates

endmodule