9. XOR Gate Using Basic Gates

How do you plan to solve it?

module and_gate(input a,b,output y);
assign y=a&b;
endmodule
module or_gate(input a,b,output y);
assign y=a|b;
endmodule
module not_gate(input a,output y);
assign y=~a;
endmodule
module xor_gate(input a,b,output y);
wire y1,y2,y3,y4;
not_gate u1(
.a(a),
.y(y1)
);
not_gate u2(
    .a(b),
    .y(y2)
);
and_gate u3(
    .a(y1),
    .b(b),
    .y(y3)
);
and_gate u4(
    .a(a),
    .b(y2),
    .y(y4)
);
or_gate uut(
    .a(y3),
    .b(y4),
    .y(y)
);
endmodule