9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire nota, notb, aandnotb, bandnota;

    // TODO: instantiate required gates
    //assign y = ~a & b | a & ~b;

    //and_gate u1 (.a(), .b(), .y());
    //or_gate u1 (.a(), .b(), .y());
    //not_gate u1 (.a(), .y());
    
    not_gate u1 (.a(a), .y(nota));
    not_gate u2 (.a(b), .y(notb));

    and_gate u3 (.a(a), .b(notb), .y(aandnotb));
    and_gate u4 (.a(nota), .b(b), .y(bandnota));

    or_gate u5 (.a(aandnotb), .b(bandnota), .y(y));

endmodule