9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w0, w1, w2, w3;

    // TODO: instantiate required gates
    not_gate n1 (.a(a), .y(w0));
    not_gate n2 (.a(b), .y(w1));
    and_gate a1 (.a(a), .b(w1), .y(w2));
    and_gate a2 (.a(w0), .b(b), .y(w3));
    or_gate o3 (.a(w2), .b(w3), .y(y));

endmodule