9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
wire nA, nB, and1, and2;

not_gate n1(a,nA);
not_gate n2(b,nB);

and_gate a1(a,nB,and1);
and_gate a2(b,nA,and2);

or_gate o1(and1,and2,y);
    // TODO: instantiate required gates

endmodule