9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a|b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire a_not_b,a_b_not,a_not,b_not;
not_gate not_a_gate(.a(a),.y(a_not));    
not_gate not_b_gate(.a(b),.y(b_not));

and_gate and1(.a(a),.b(b_not),.y(a_b_not));
and_gate and2(.a(b),.b(a_not),.y(a_not_b));

or_gate or_out(.a(a_b_not),.b(a_not_b),.y(y));
    // TODO: instantiate required gates

endmodule