9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire x1, x2; //not outputs
    wire y1,y2; //and

    not_gate a1(.a(a),.y(x1));
    not_gate b1(.a(b),.y(x2));

    and_gate u1(.a(a),.b(x2),.y(y1));
    and_gate u2(.a(x1),.b(b),.y(y2));

    or_gate u3(.a(y1),.b(y2),.y(y));

    // TODO: instantiate required gates

endmodule