9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
 assign  y = a|b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
wire w1,w2,w3,w4;
not_gate uut1(.a(a),.y(w1));
not_gate uut2(.a(b),.y(w2));
and_gate uut3(.a(w1),.b(b),.y(w3));
and_gate uut4(.a(w2),.b(a),.y(w4));
or_gate uut5(.a(w3),.b(w4),.y(y));


    // TODO: declare intermediate wires

    // TODO: instantiate required gates

endmodule