9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w0, w1;

    // TODO: instantiate required gates
    and_gate a1(.a(a), .b(~b), .y(w0));
    and_gate a2(.a(~a), .b(b), .y(w1));
    or_gate a3(.a(w0), .b(w1), .y(y));

endmodule