9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output reg y);
    // write code here for or gate
    always@(*)
    begin
    y=a|b;
    end

endmodule

module not_gate(input a, output reg y);
    // write code here for not gate
    always@(*)
    begin
        y=~a;
    end

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output reg y
);
    // TODO: declare intermediate wires

    // TODO: instantiate required gates
    always@(*)
    begin
    y=(~a&b)|(a&~b);
    end

endmodule