9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
   assign y=a|b;

endmodule

module not_gate(input a, output y);
    assign y=~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    wire t1,t2;
    wire nota,notb;
    not_gate n1(.a(a),.y(nota));
    not_gate n2(.a(b),.y(notb));
    and_gate a1(.a(a),.b(notb),.y(t1));
    and_gate a2(.a(nota),.b(b),.y(t2));
    or_gate o1(.a(t1),.b(t2),.y(y));

    // TODO: instantiate required gates

endmodule