9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
assign y= a||b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
assign y=!a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
wire nota,notb,notab,notba;
    // TODO: instantiate required gates
not_gate notgatea (.a(a),.y(nota));
not_gate notgateb (.a(b),.y(notb));
and_gate andbar (.a(a),.b(notb),.y(notba));
and_gate andabar (.a(nota),.b(b),.y(notab));
or_gate or_gate1(.a(notab),.b(notba),.y(y));


endmodule