9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
   assign y=a|b; // write code here for or gate

endmodule

module not_gate(input a, output y);
  assign y=~a;  // write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
   wire nota, notb, t1, t2; // TODO: declare intermediate wires
and_gate a1(.a(a),.b(notb),.y(t1));
and_gate a2(.a(b),.b(nota),.y(t2));   // TODO: instantiate required gates
not_gate n1(.a(b),.y(notb));
not_gate n2(.a(a),.y(nota));
or_gate o1(.a(t1),.b(t2),.y(y));
endmodule