9. XOR Gate Using Basic Gates

How do you plan to solve it?

// Basic Gates (given)
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;
 endmodule

module not_gate(input a, output y);
     assign y = ~a;
endmodule

// XOR Gate
module xor_gate(
    input a, b,
    output y
 );
// Intermediate wires
    wire nota, notb;
    wire aandnotb, notaandb;

 // Instantiate NOT gates
    not_gate u1(.a(a), .y(nota));
    not_gate u2(.a(b), .y(notb));

 // Instantiate AND gates
    and_gate u3(.a(a), .b(notb), .y(aandnotb));
    and_gate u4(.a(nota), .b(b), .y(notaandb));

// Instantiate OR gate
    or_gate u5(.a(aandnotb), .b(notaandb), .y(y));

 endmodule