9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;
endmodule

module not_gate(input a, output y);
   assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire nota, notb, anb, nab;
    // TODO: instantiate required gates
    not_gate not1(a, nota);
    not_gate not2(b, notb);
    and_gate and1(a, notb, anb);
    and_gate and2(b, nota, nab);
    or_gate  or1(nab, anb, y);


endmodule