9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire notai,notbi,andai,andbi;
    // TODO: instantiate required gates
    not_gate nota ( .a(a), .y(notai));
    not_gate notb ( .a(b), .y(notbi));
    and_gate anda (.a(a),.b(notbi),.y(andai));
    and_gate andb (.a(b),.b(notai),.y(andbi));
    or_gate or0 (.a(andai),.b(andbi),.y(y));   

endmodule