9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w0, w1, n_a, n_b;
    // TODO: instantiate required gates
    not_gate not_a (a, n_a);
    not_gate not_b (b, n_b);

    and_gate and0 (a, n_b, w0);
    and_gate and1 (n_a, b, w1);

    or_gate res (w0, w1, y);
endmodule