XOR Gate Using Basic Gates

Solving Approach

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Code

// Basic Gates
module and_gate(input a, input b, output y);
    assign y = a & b;
    endmodule

    module or_gate(input a, input b, output y);
        assign y = a | b;
        endmodule

        module not_gate(input a, output y);
            assign y = ~a;
            endmodule

            // XOR Gate using basic gates
            module xor_gate(input a, input b, output y);
                wire n_a, n_b;
                    wire and1_out, and2_out;

                        not_gate not_a(.a(a), .y(n_a));
                            not_gate not_b(.a(b), .y(n_b));

                                and_gate and1(.a(a), .b(n_b), .y(and1_out));
                                    and_gate and2(.a(n_a), .b(b), .y(and2_out));

                                        or_gate or1(.a(and1_out), .b(and2_out), .y(y));
                                        endmodule

 

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Testbench Code

`timescale 1ns/1ps

module tb_xor_gate;
    // Inputs
    reg a, b;
    // DUT output
    wire y;
    // Expected output
    reg expected_y;

    // Mismatch flag
    wire mismatch = (y !== expected_y);

    // Counters
    integer TOTAL_TEST_CASES = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // DUT
    xor_gate dut (.a(a), .b(b), .y(y));

    // VCD: only inputs, output, expected, mismatch
    initial begin
        $dumpfile("tb_xor_gate.vcd");
        $dumpvars(0,
            tb_xor_gate.a, tb_xor_gate.b,
            tb_xor_gate.y,
            tb_xor_gate.expected_y,
            tb_xor_gate.mismatch
        );
    end

    // Apply, check, and print ONE row (no duplicate driving)
    task run_and_show;
        input ta, tb_;
        begin
            a = ta; b = tb_;
            expected_y = ta ^ tb_;
            #1; // settle

            TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
            if (!mismatch)
                TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
            else
                TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;

            $display("%b %b | %b | %b | %b", a, b, y, expected_y, mismatch);
        end
    endtask

    initial begin
        $display("a b | y | expected_y | mismatch");
        $display("--------------------------------");

        // Truth table — each case executed exactly once
        run_and_show(0,0);
        run_and_show(0,1);
        run_and_show(1,0);
        run_and_show(1,1);

        // Summary
        $display("======================================");
        $display("TOTAL_TEST_CASES=%0d",        TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
        $display("======================================");

        $finish;
    end
endmodule