9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y=a|b;

endmodule

module not_gate(input a, output y);
    assign y=~a;

endmodule


module xor_gate (
    input  a, b,
    output y
);
    wire nota,notb,and0,and1;
    not_gate n0 (.a(a),.y(nota));
    not_gate n1 (.a(b),.y(notb));
    and_gate a0 (.a(a),.b(notb),.y(and0));
    and_gate a1 (.a(nota),.b(b),.y(and1));
    or_gate o0 (.a(and0),.b(and1),.y(y));
endmodule