9. XOR Gate Using Basic Gates

How do you plan to solve it?

// // Basic Gate Modules
module and_gate(input a, input b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, input b, output y);
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    assign y = ~a;
endmodule


// XOR Gate built using basic gates
module xor_gate(input a, input b, output y);
    wire nota, notb;
    wire and1_out, and2_out;

    // Instantiate NOT gates
    not_gate u1(.a(a), .y(nota));
    not_gate u2(.a(b), .y(notb));

    // Instantiate AND gates
    and_gate u3(.a(a), .b(notb), .y(and1_out));
    and_gate u4(.a(nota), .b(b), .y(and2_out));

    // Instantiate OR gate
    or_gate u5(.a(and1_out), .b(and2_out), .y(y));
endmodule