9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;
    // write code here for or gate

endmodule

module not_gate(input a, output y);
    assign y = ~a;

    // write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
); 
   wire w1,w2,w3,w4;
   not_gate s3 (.a(a),.y(w1));
   not_gate s4 (.a(b),.y(w2));

   and_gate s1 (.a(b),.b(w1),.y(w3));
   and_gate s2 (.a(a),.b(w2),.y(w4));
   or_gate s5 (.a(w3),.b(w4),.y(y));
    // TODO: declare intermediate wires

    // TODO: instantiate required gates

endmodule