9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;    
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~ a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire n1, n2, n3, n4;
    not_gate no1(a, n1);
    not_gate no2(b, n2);
    and_gate a1(n1 , b , n3);
    and_gate a2(n2 , a , n4);
    or_gate or1(n3, n4, y);     
    // TODO: instantiate required gates

endmodule