9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
   assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire abar,bbar;
    wire and1,and2;
    // TODO: instantiate required gates
    not_gate a0(a,abar);
    not_gate b0(b,bbar);
    and_gate a1(a,bbar,and1);
    and_gate a2(b,abar,and2);
    or_gate o(and1,and2,y);

endmodule